1. Field of the Invention
The invention relates in general to voltage measurement such as in analog-to-digital converters and in particular to low-power, high-speed analog-to-digital converters.
2. Statement of the Problem
Analog-to-digital converters (ADCs) are used in electronic systems where signals produced by sensors (such as microphones, temperature probes, light sensors, and speed or position transducers) or activators (such as voltage sources and amplifiers) are analog voltages, and where processing is performed in the digital domain. Some characteristics of an ADC include the analog input voltage range; the resolution, which is typically the analog voltage corresponding to the least significant bit (LSB); the conversion time (the time it takes to update the digital output for a given analog input voltage); and the linearity of the ADC input-to-output characteristic.
In digitally controlled power supplies, the ADC is typically used to sample an output voltage (or some other voltage or current of interest) of a device and compare it to a reference voltage to produce a digital error signal indicative of the difference between the compared voltages. In direct-current (DC) power supplies, the voltage reference is typically a constant voltage independent of temperature.
Nyquist-rate ADCs form one existing category of ADCs. These ADCs typically sample at twice the frequency of the highest frequency component of the input being sampled. The characteristics of a selection of Nyquist-rate ADCs are discussed below.
A successive approximation ADC receives an analog voltage as a first input into a differential comparator. The comparator output, in turn, provides a control signal to a counter which then outputs a digital value corresponding to a “first round” approximation of the magnitude of the received analog voltage. This digital value is then fed into a digital-to-analog converter (DAC), which completes a feedback path by supplying a second input to the differential comparator. The comparator compares the analog input voltage to the analog quantity output from the DAC. The comparator output then causes the counter to raise or lower the DAC output to more closely match the analog input voltage. A significant drawback of the successive approximation ADC is that it is slow to reach a steady-state output value.
Where speed is of paramount concern, a flash converter, also known as a parallel converter, may be employed. The flash ADC is distinctive in having a conversion time of less than a single clock cycle. The converter includes a plurality of differential comparators with each comparator being dedicated to a particular voltage level. Each comparator is supplied with a common input voltage and a distinct reference voltage using a voltage-divider network. Although it offers the advantage of rapid conversion time, the flash ADC is limited by its high power consumption, susceptibility to noise, and the need for large die areas.
The “windowed” flash ADC offers higher resolution than the standard flash ADC by concentrating a disproportionate number of comparators within a voltage range of interest. While this approach offers greater resolution than the standard flash ADC, a large number of analog comparators is required, thereby exacerbating the problems of power consumption and large die area requirements of the standard flash ADCs.
The conversion accuracy of flash ADCs is a strong function of the accuracy of the values of resistors used in voltage dividers and of the characteristics of the analog comparators used to provide each output bit. Accordingly, careful design and/or selection of these devices is needed to ensure accurate conversion accuracy. One variation of the flash ADC uses digital error correction to compensate for variation inherent in the resistors and comparators. Although this approach improves the accuracy of flash converters, the drawbacks of a high power requirement and large required die area remain.
Over-sampling ADCs offer a less noisy solution than Nyquist-rate converters. With Nyquist-rate converters, quantization noise arising from conversion of an analog input signal is typically concentrated within a limited frequency range. The higher sampling frequency of over-sampling ADCs spreads the noise power over a much larger spectrum. Consequently, the proportion of quantization noise within the frequency band of the analog input signal is lower in over-sampling ADCs than in Nyquist-rate ADCs. Transmitting the noisy signal through a low-pass filter (LPF), therefore, can substantially reduce noise in the digital output. However, over-sampling ADCs require very high power consumption to support the high sampling frequencies employed.
Thus, there is a need for an ADC that operates at high speed while utilizing low power and, at the same time, has low die area and does not depend on the precision of individual analog components.